Duration and Audience:

Full day workshop, HPC Tool Developers, Architects, and Performance Modelers and Analysts

Format (tenative):

Invited talks and selected 15 minute “Position Presentations” followed by focused discussions.

Call for Participation:

Please send a single page abstract for your position presentation to mlang@lanl.gov by October 27th.

Important Dates (tenative):

Position Abstracts due: October 27, 2006

Author Notifications: November 9, 2006

Conference Dates: Saturday, December 9-13, 2006

Program (TBA)

Contact: Mike Lang, mlang@lanl.gov, 505-665-5756

Call for Participation

The workshop of the Functionality of Hardware Performance Monitors is a forum to bring together a community consisting of the designers of HPMs, developers and researchers of software tools that use HPMs, and those who use these tools to evaluate systems and applications. The intent of bringing designers and users together in this venue is to positively influence development in this area. In particular, there is a pressing need for future convergence between the needs and expectations of HPM users and the possibilities and constraints placed on hardware designs.

This one-day workshop invites participation from chip designers/architects, tool developers, experts in performance analysis, and model developers. The speakers will be asked to give presentations that elicit ideas and reaction rather than simply provide current project information. Guided discussion session sessions with broad participation by all participants will be a major part of the final agenda.

A previous workshop (See http://lacsi.rice.edu/workshops/hpca11.) addressed the design and use of HPMs in the current generation of microprocessors. In addition to this core issue, we are especially interested in presentations that address the following issues:

• HPM issues with Chip Multi-Processing (CMP) and Simultaneous Multi-Threading (SMT)

• HPM’s uses in performance modeling (memory system models, execution models, …)

• Off core/chip monitors (memory, bus, memory hub controller(MHC) …)

• Operating system interface to HPM’s

• Network HPM’s

• New HPM features

• Current HPM deficiencies

• HPM for Power management

• Novel uses for HPM

The tangible result of the workshop will be a web site that will contain presentation materials, useful resources, and summaries of the discussions and recommendations of the participants. This site is intended to be used as a reference for designers of future chip sets and supporting software engineers. We will implement a wiki to allow the attendees and workshop recorders to comment on each talk and the discussions in real-time as well as after the end of the workshop.